Germanium-on-insulator (GeOI) finFET structures have been developed to increase carrier mobility for pFET and nFET, as well as to reduce sub-fin leakage current due to the use of a bottom insulator layer directly under the channel fin. However, a pure GeOI finFET structure, formed with 100% germanium (Ge) in the entire finFET structure, may have increased off-state leakage due to band-to-band-tunneling (BTBT) associated with a small bandgap of pure Ge. One approach to reduce BTBT leakage is to add silicon (Si) to the Ge film to form a SiGe material composition. The SiGe material composition may have an increased bandgap that may significantly reduce the BTBT leakage. However, adding a constant percentage of Si throughout the entire GeOI finFET may result in overall lower channel mobility than desired and thus worse performance of the GeOI finFET structure.
Reference is now made to FIG. 1 which is a cross sectional view schematically illustrating a conventional GeOI finFET semiconductor device. A conventional GeOI finFET semiconductor device 100 may include a substrate 105 and an insulator layer 110 disposed on the substrate 105. The conventional GeOI finFET semiconductor device 100 may also include a channel region 120 having a fin shape. The conventional GeOI finFET semiconductor device 100 may include a gate stack 150 on a top surface of the channel region 120 and extending down sidewall surfaces of the fin. Regions on sides of the channel region 120 may be removed by a recess etch and a source region 130 and a drain region 140 may be epitaxially regrown in the recessed regions on opposing sides of the channel region 120. The source region 130 and drain region 140 may include a higher percentage of Si than the channel region 120 to reduce the BTBT leakage and increase performance. However, the insulator layer 110 may not be lattice matched to the epitaxial material of the source region 130 and the drain region 140. If the recess etch is a full recess etch to the insulator layer 110, there may be no remaining fin material at the bottom to serve as a template for epitaxial re-growth of SiGe of a higher percentage of Si to refill the recessed regions. Therefore, a partial recess etch may leave regions of fin material, 160 and 170, between the insulator layer 110 and the source and drain regions, 130 and 140, respectively. However, as the regions of fin material, 160 and 170, may have a lower percentage of Si than source and drain regions, 130 and 140, a bottom of the finFET structure may provide higher BTBT leakage.
Reference is now made to FIGS. 2A and 2B which are a cross sectional view schematically illustrating another conventional GeOI finFET semiconductor device and a cross-sectional view taken along the line A-A′ of FIG. 2A, respectively. A conventional GeOI finFET semiconductor device 200 may include a substrate 205 and an insulator layer 210 disposed on the substrate 205. The conventional GeOI finFET semiconductor device 200 may also include a channel region 220 having a fin shape. The conventional GeOI finFET semiconductor device 200 may include a gate stack 250 on a top surface of the channel region 220 and extending down sidewall surfaces of the fin. A source region 230 and a drain region 240 may be epitaxially grown around the fin on opposing sides of the channel region 220. The source and drain regions, 230 and 240, may include a higher percentage of Si than the channel region 220 to reduce the BTBT leakage and increase performance. However, as the regions of fin material that source and drain regions, 230 and 240, are grown around may have a lower percentage of Si than source and drain regions, 130 and 140, a bottom of the finFET structure, or substantially the entire finFET structure, may provide higher BTBT leakage.